參數(shù)資料
型號: ST16C550
廠商: Exar Corporation
英文描述: UART with 16-Byte FIFO(通用異步接收器/發(fā)送器(帶16字節(jié)的先進先出))
中文描述: 的UART具有16字節(jié)FIFO(通用異步接收器/發(fā)送器(帶16字節(jié)的先進先出))
文件頁數(shù): 13/36頁
文件大?。?/td> 235K
代理商: ST16C550
ST16C550
13
Rev. 4.20
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 4, ST16C550 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *2
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
0
THR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
IER [00]
0
0
0
0
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
0
1
0
FCR [00]
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
0
0
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
0
1
0
ISR [01]
FIFO’s
enabled
FIFO’s
enabled
0
0
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
0
1
1
LCR [00]
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
1
0
0
MCR [00]
0
0
0
loopback
enable
-OP2
-OP1
-RTS
-DTR
1
0
1
LSR [60]
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
0
MSR [X0]
CD
RI
DSR
CTS
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
1
1
1
SPR [FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1.
Note 1*
0
0
0
DLL [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
DLM [XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1.
Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.
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