參數(shù)資料
型號: ST16C2451
廠商: Exar Corporation
英文描述: 2.97V TO 5.5V DUART
中文描述: 2.97V至5.5V杜阿爾特
文件頁數(shù): 7/29頁
文件大?。?/td> 315K
代理商: ST16C2451
á
REV. 4.0.0
ST16C2450
2.97V TO 5.5V DUART
7
2.3
The UART provides the user with the capability to bi-directionally transfer information between an external CPU
and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the user to
select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART.
Selecting both UARTs can be useful during power up initialization to write to the same internal registers, but do
not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1
.
Channel A and B Selection
2.4
Each UART channel in the 2450 has a standard register set for controlling, monitoring and data loading and
unloading. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratch pad register
(SPR).
2.5
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 2
summarizes the operating behavior for the transmitter and receiver. Also see
Figure 12
and
Figure 13
.
Channel A and B Internal Registers
2.6
The 2450 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output.
See “Programmable Baud Rate
Generator” on page 8.
Crystal Oscillator or External Clock Input
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
CSA#
CSB#
F
UNCTION
1
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
0
Channel A and B selected
T
ABLE
2: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
T
RANSMITTER
R
ECEIVER
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = no data
1 = 1 byte
相關(guān)PDF資料
PDF描述
ST16C2552CJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552IJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST162552 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C2552IJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
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