參數(shù)資料
型號: ST16C2451
廠商: Exar Corporation
英文描述: 2.97V TO 5.5V DUART
中文描述: 2.97V至5.5V杜阿爾特
文件頁數(shù): 10/29頁
文件大?。?/td> 315K
代理商: ST16C2451
ST16C2450
2.97V TO 5.5V DUART
á
REV. 4.0.0
10
2.9
The receiver section contains an 8-bit Receive Shift Register (RSR) and 1 byte FIFO or Receive Holding
Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming
character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver
counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the
start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Once the data is received, the error tags are immediately updated to
reflect the status of the data byte in RHR register. RHR will generate a receive data ready interrupt upon
receiving a character if IER bit-0 has been enabled.
2.9.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register.
It provides the receive data interface to the host processor. The RHR register is part of the 1 byte receive FIFO
that is 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. After the RHR is read,
LSR bits 2-4 willl immediately be updated to reflect the errors for the next character byte transferred from the
RSR.
Receiver
F
IGURE
6. R
ECEIVER
O
PERATION
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
相關(guān)PDF資料
PDF描述
ST16C2552CJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552IJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST162552 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C2552IJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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