參數(shù)資料
型號: ST16C2451
廠商: Exar Corporation
英文描述: 2.97V TO 5.5V DUART
中文描述: 2.97V至5.5V杜阿爾特
文件頁數(shù): 11/29頁
文件大?。?/td> 315K
代理商: ST16C2451
á
REV. 4.0.0
ST16C2450
2.97V TO 5.5V DUART
11
2.10
The 2450 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode
is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 7
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
Internal Loopback
F
IGURE
7. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNELS
A
AND
B
TXA/TXB
RXA/RXB
M
I
RTSA#/RTSB#
MCR bit-4=1
VCC
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
VCC
相關(guān)PDF資料
PDF描述
ST16C2552CJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552IJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST162552 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C2552IJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
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