參數(shù)資料
型號： ST16C2451
廠商： Exar Corporation
英文描述： 2.97V TO 5.5V DUART
中文描述： 2.97V至5.5V杜阿爾特
文件頁數(shù)： 14/29頁
文件大?。?/td> 315K
代理商： ST16C2451
ST16C2450
2.97V TO 5.5V DUART
á
REV. 4.0.0
14
4.3.1
When the receive interrupt (IER BIT-0 = 1) is enabled, the RHR interrupt (see ISR bit-2) status will reflect the
following:
A.
The receive data available interrupts are issued to the host when there is a character in the RHR. It will be
cleared when the character has been read out of the RHR.
B.
The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the RHR is empty.
4.3.2
Polled Mode Operation
Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode
by selecting respective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in the RHR.
B.
LSR BIT-1 indicates an overrun error has occurred and that data in the RHR may not be valid.
C.
LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D.
LSR BIT-5 indicates THR is empty.
E.
LSR BIT-6 indicates when both the THR and TSR are empty.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
Table 6
, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
Interrupt Mode Operation
相關PDF資料
PDF描述
ST16C2552CJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552IJ44 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST162552 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C2552IJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
相關代理商/技術參數(shù)
參數(shù)描述
ST16C2550 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO
ST16C2550_04 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO
ST16C2550CJ-0A-EB 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
ST16C2550CJ44 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO
ST16C2550CJ44-F 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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