參數(shù)資料
型號: ST162552
廠商: Exar Corporation
英文描述: DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
中文描述: 雙異步接收器/發(fā)送器與FIFO的
文件頁數(shù): 8/28頁
文件大?。?/td> 121K
代理商: ST162552
3-142
ST16C2552
S
*RECEIVE TIME-OUT:
This mode is enabled when STARTECH UART is
operating in FIFO mode. Receive time out will not
occur if the receive FIFO is empty. The time out
counter will be reset at the center of each stop bit
received or each time receive holding register is read.
The actual time out value is T (
T
ime out length in
bits)= 4 X P (
P
rogrammed word length) + 12. To
convert time out value to a character value, user has
to divide this number to its complete word length +
parity ( if used) + number of stop bits and start bit.
Example -A: If user programs the word length = 7, and
no parity and one stop bit, Time out will be:
T = 4 X 7( programmed word length) +12 = 40 bits
Character time = 40 / 9 [ (programmed word length =
7) + (stop bit = 1) + (start bit = 1)] = 4.4 characters.
Example -B: If user programs the word length = 7, with
parity and one stop bit, the time out will be:
T = 4 X 7(programmed word length) + 12 = 40 bits
Character time = 40 / 10 [ (programmed word length
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
ISR BIT-0:
0=an interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service
routine.
1=no interrupt pending.
ISR BIT 1-3:
Logical combination of these bits, provides the high-
est priority interrupt pending.
ISR BIT 4-7:
These bits are not used and are set to zero if the FIFOs
are not enabled.
BIT 6-7:
are set to “1” when the FIFOs
are enabled.
FIFO CONTROL REGISTER (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the receiver FIFO trigger level, and select
the type of DMA signaling.
FCR BIT-0:
0=Disable the transmit and receive FIFO.
1=Enable the transmit and receive FIFO.
IER BIT-1:
0=disable the transmitter empty interrupt.
1=enable the transmitter empty interrupt.
IER BIT-2:
0=disable the receiver line status interrupt.
1=enable the receiver line status interrupt.
IER BIT-3:
0=disable the modem status register interrupt.
1=enable the modem status register interrupt.
IER BIT 4-7:
All these bits are set to logic zero.
INTERRUPT STATUS REGISTER (ISR)
The ST16C2552 provides four level prioritized inter-
rupt conditions to minimize software overhead during
data character transfers. The Interrupt Status Regis-
ter (ISR) provides the source of the interrupt in priori-
tized matter. During the read cycle the ST16C2552
provides the highest interrupt level to be serviced by
CPU. No other interrupts are acknowledged until the
particular interrupt is serviced. The following are the
prioritized interrupt levels:
Priority level
P
D3
D2
D1
D0
Source of the interrupt
1
0
1
1
0
LSR (Receiver Line Sta-
tus Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time out)
TXRDY( Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
2
0
1
0
0
2*
1
1
0
0
3
0
0
1
0
4
0
0
0
0
相關(guān)PDF資料
PDF描述
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C2552IJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C452IJ68 DUAL UART WITH PARALLEL PRINTER PORT
ST16C452IJ68PS DUAL UART WITH PARALLEL PRINTER PORT
ST16C452CJ68 Power Supply IC; Number of Outputs:1; Supply Voltage Max:5.5V; Package/Case:10-MSOP; Leaded Process Compatible:No; Output Current:150mA; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Power Dissipation:481mW
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST1638 制造商:STANSON 制造商全稱:STANSON 功能描述:Step-Up DC/DC Converter High Efficiency PFM
ST1638-XXS23 制造商:STANSON 制造商全稱:STANSON 功能描述:Step-Up DC/DC Converter High Efficiency PFM
ST1638-XXS89 制造商:STANSON 制造商全稱:STANSON 功能描述:Step-Up DC/DC Converter High Efficiency PFM
ST163D00 功能描述:撥動(dòng)開關(guān) TOGGLE RoHS:否 制造商:C&K Components 觸點(diǎn)形式:DPDT 開關(guān)功能:ON - ON - ON 電流額定值: 電壓額定值 AC:20 V 電壓額定值 DC:20 V 功率額定值:0.4 VA 端接類型:V-Bracket 安裝風(fēng)格: 端子密封:Epoxy 觸點(diǎn)電鍍:Gold 照明:Not Illuminated
ST163X377 制造商:Allied Controls Incorporated 功能描述: