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參數(shù)資料
| 型號(hào)： | ST162552 |
| 廠商： | Exar Corporation |
| 英文描述： | DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs |
| 中文描述： | 雙異步接收器/發(fā)送器與FIFO的 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大小： | 121K |
| 代理商： | ST162552 |
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3-137
ST16C2552
S
Symbol
Pin
Signal Type
Pin Description
SYMBOL DESCRIPTION
D0-D7
2-9
I/O
Bi-directional data bus. Eight bit, three state data bus to
transfer information to or from the CPU. D0 is the least
significant bit of the data bus and the first serial data bit to
be received or transmitted.
RX A/B
39,25
I
Serial data input A/B. The serial information (data) received
from serial port to ST16C2552 receive input circuit. A mark
(high) is logic one and a space (low) is logic zero. During the
local loopback mode the RX input is disabled from external
connection and connected to the TX output internally.
TX A/B
38,26
O
Serial data output A/B. The serial data is transmitted via
this pin with additional start , stop and parity bits. The TX will
be held in mark (high) state during reset, local loopback
mode or when the transmitter is disabled.
CS*
18
I
Chip select. (active low) A low at this pin enables the
ST16C2552 / CPU data transfer operation.
CHSEL
16
I
UART A/B select. UART A or B can be selected by changing
the state of this pin when CS* is active. Low on this pin,
selects the UART B and high on this pin selects UART A
section.
XTAL1
11
I
Crystal input 1 or external clock input. A crystal can be
connected to this pin and XTAL2 pin to utilize the internal
oscillator circuit. An external clock can be used to clock
internal circuit and baud rate generator for custom transmis-
sion rates.
XTAL2
13
O
Crystal input 2 or buffered clock output. See XTAL1.
Should be left open if a clcok is connected to XTAL1.
IOW*
20
I
Write strobe. (active low) A low on this pin will transfer the
contents of the CPU data bus to the addressed register.
IOR*
24
I
Read strobe. (active low) A low level on this pin transfers
the contents of the ST16C2552 data bus to the CPU.
A0-A2
10,14,15
I
Address select lines. To select internal registers.
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