參數(shù)資料
型號(hào)： ST162552
廠商： Exar Corporation
英文描述： DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
中文描述： 雙異步接收器/發(fā)送器與FIFO的
文件頁數(shù)： 12/28頁
文件大?。?/td> 121K
代理商： ST162552
3-146
ST16C2552
S
MSR BIT-0:
Indicates that the CTS* input to the ST16C2552 has
changed state since the last time it was read.
MSR BIT-1:
Indicates that the DSR* input to the ST16C2552 has
changed state since the last time it was read.
MSR BIT-2:
Indicates that the RI* input to the ST16C2552 has
changed from a low to a high state.
MSR BIT-3:
Indicates that the CD* input to the ST16C2552 has
changed state since the last time it was read.
MSR BIT-4:
This bit is equivalent to RTS in the MCR during local
loop-back mode. It is the compliment of the CTS*
input.
MSR BIT-5:
This bit is equivalent to DTR in the MCR during local
loop-back mode. It is the compliment of the DSR*
input.
MSR BIT-6:
This bit is equivalent to OP1 in the MCR during local
loop-back mode. It is the compliment of the RI* input.
MSR BIT-7:
This bit is equivalent to OP2 in the MCR during local
loop-back mode. It is the compliment to the CD* input.
Note: Whenever MSR BIT3-0: is set to logic “1”, a
MODEM Status Interrupt is generated.
SCRATCHPAD REGISTER (SR)
ST16C2552 provides a temporary data register to
store 8 bits of information for variable use.
BAUD RATE GENERATOR PROGRAMMING
TABLE (1.8432 MHz CLOCK):
BAUD RATE
16 x CLOCK
DIVISOR
% ERROR
50
75
150
300
600
1200
2400
4800
7200
9600
19.2K
38.4K
56K
115.2K
2304
1536
768
384
192
96
48
24
16
12
6
3
2
1
2.77
ST16C2552 EXTERNAL RESET CONDITION
REGISTERS
RESET STATE
IER
ISR
LCR
MCR
LSR
IER BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7=input signals
FCR BITS 0-7=0
AFR BITS 0-7=0
MSR
FCR
MFR
SIGNALS
RESET STATE
TX
OP2*
RTS*
DTR*
INT
TXRDY*
High
High
High
High
Low
Low
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