參數(shù)資料
型號: SST49LF008C-33-4C-NHE
元件分類: PROM
英文描述: 1M X 8 FLASH 3V PROM, 11 ns, PQCC32
封裝: ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32
文件頁數(shù): 6/36頁
文件大?。?/td> 509K
代理商: SST49LF008C-33-4C-NHE
14
Advance Information
4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
200 Silicon Storage Technology, Inc.
S71292-00-000
1/06
Firmware Memory Write Cycle
FIGURE 6: FIRMWARE MEMORY WRITE CYCLE WAVEFORM
TABLE
5: FIRMWARE MEMORY WRITE CYCLE
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]1
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction
Comments
1
START
1110
IN
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) will be recognized. The START field contents
(1110b) indicate a Firmware Memory Write cycle.
2
IDSEL
0000 to 1111
IN
Indicates which
SST49LF00xC device should
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], then that particular device will respond
to the whole bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
10
MSIZE
KKKK
IN
The MSIZE field indicates how many bytes will be
transferred during multi-byte operations.
Device supports 1, 2, and 4 Bytes write with MSIZE =
0, 1, or 2, and KKKK=0000b, 0001b, or 0010b.
11-A
DATA
ZZZZ
IN
A=(10+2n+1); n = MSIZE
Least significant nibble entered first.
(A+1)
TAR0
1111
IN then Float
In this clock cycle, the master (Intel ICH) has driven the
bus to all ‘1’s and then floats the bus prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.” A=(10+2n+1); n = MSIZE
(A+2)
TAR1
1111 (float)
Float then OUT
The
SST49LF00xC takes control of the bus during this
cycle.
A=(10+2n+1); n = MSIZE
(A+3)
RSYNC
0000
OUT
During this clock cycle, the
SST49LF00xC generates
a “ready sync” (RSYNC) and outputs the values 0000,
indicating that it has received data or a flash command.
A=(10+2n+1); n = MSIZE
(A+4)
TAR0
1111
OUT then Float
In this clock cycle, the
SST49LF00xC drives the bus to
all ‘1’s and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle”. A=(10+2n+1); n = MSIZE
(A+5)
TAR1
1111 (float)
Float then IN
The host resumes control of the bus during this cycle.
A=(10+2n+1); n = MSIZE
T5.0 1292
1292 F04.0
LFRAME#
LAD[3:0]
1110b
0000b
A[23:20] A[19:16]
A[3:0]
A[7:4]
A[11:8]
A[15:12]
MADDR
Start
IDSEL
MSIZE
LCLK
A[27:24]
0000b
RSYNC
TAR1
TAR0
TAR
D0[7:4]
Tri-State
D0[3:0]
Dn[7:4]
Dn[3:0]
KKKKb
1111b
DATA
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