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參數(shù)資料
| 型號： | SST49LF008C-33-4C-NHE |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 5/36頁 |
| 文件大?。?/td> | 509K |
| 代理商： | SST49LF008C-33-4C-NHE |
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Advance Information
4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
13
200 Silicon Storage Technology, Inc.
S71292-00-000
1/06
FIRMWARE MEMORY CYCLES
Firmware Memory Read Cycle
FIGURE 5: FIRMWARE MEMORY READ CYCLE WAVEFORM
TABLE
4: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]1
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction
Comments
1
START
1101
IN
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions high)
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
2
IDSEL
0000 to 1111
IN
Indicates which
SST49LF00xC device should respond.
If the IDSEL (ID select) field matches the value of ID[3:0],
then that particular device will respond to the LPC bus
cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
10
MSIZE
KKKK
IN
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations.
Device will execute multi-byte read of 2MSIZE bytes.
SST49LF00xC supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4,
16, 128 Bytes), with KKKK=0000b, 0001b, 0010b, 0100b, or
0111b.
11
TAR0
1111
IN,
then Float
In this clock cycle, the master (Intel ICH) has driven the bus
to all ‘1’s and then floats the bus, prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float,
then OUT
The
SST49LF00xC takes control of the bus during this
cycle.
13
RSYNC
0000 (READY)
OUT
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data. The least-significant nibble of the least-significant byte
will be available during the next clock cycle.
14-A
DATA
ZZZZ
OUT
A=(13+2n+1); n = MSIZE
Least significant nibbles outputs first.
(A+1)
TAR0
1111
OUT,
then Float
In this clock cycle, the
SST49LF00xC drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
A=(13+2n+1); n = MSIZE
(A+2)
TAR1
1111 (float)
Float,
then IN
The host resumes control of the bus during this cycle.
A=(13+2n+1); n = MSIZE
T4.0 1292
1292 F03.0
LFRAME#
LAD[3:0]
1101b
0000b
A[23:20] A[19:16]
A[3:0]
A[7:4]
A[11:8]
A[15:12]
MADDR
Start
IDSEL
MSIZE
LCLK
A[27:24]
0000b
RSYNC
TAR1
TAR0
TAR
D0[7:4]
Tri-State
D0[3:0]
Dn[7:4]
Dn[3:0]
KKKKb
1111b
DATA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST49LF008C-33-4C-WHE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash |
| SST49LF016C | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit LPC Serial Flash |
| SST49LF016C-33-4C-EIE | 功能描述:閃存 16M (2Mx8) 33MHz 3.0-3.6V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST49LF016C-33-4C-EIE-T | 功能描述:閃存 3.0 to 3.6V 16Mbit LPC Firmware 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST49LF016C-33-4C-NHE | 功能描述:閃存 16M (2Mx8) 33MHz 3.0-3.6V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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