參數(shù)資料
型號(hào)： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 47/73頁(yè)
文件大?。?/td> 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
RESET TIMING
timing requirements for reset (see Figure 26)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
1
tw(RST)
Width of the RESET pulse (PLL stable)
10*
10
CLKOUT1
cycles
μ
s
Width of the RESET pulse (PLL needs to sync up)
250*
250
*This parameter is not production tested.
The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250
μ
s to stabilize following device
powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the
clock PLLsection for PLL lock times.
switching characteristics during reset
(see Figure 26)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
2
tR(RST)
Response time to change of value in RESET signal
2
2
CLKOUT1
cycles
3
td(CKO1H-CKO2IV)
td(CKO1H-CKO2V)
td(CKO1H-SDCLKIV)
td(CKO1H-SDCLKV)
td(CKO1H-SSCKIV)
td(CKO1H-SSCKV)
td(CKO1H-LOWIV)
td(CKO1H-LOWV)
td(CKO1H-HIGHIV)
td(CKO1H-HIGHV)
td(CKO1H-ZHZ)
td(CKO1H-ZV)
Low group consists of:
High group consists of:
Z group consists of:
Delay time, CLKOUT1 high to CLKOUT2 invalid
–1*
10*
–1
10
ns
4
Delay time, CLKOUT1 high to CLKOUT2 valid
–1*
10
–1
10
ns
5
Delay time, CLKOUT1 high to SDCLK invalid
–1*
10*
–1
10
ns
6
Delay time, CLKOUT1 high to SDCLK valid
–1*
10
–1
10
ns
7
Delay time, CLKOUT1 high to SSCLK invalid
–1*
10*
–1
10
ns
8
Delay time, CLKOUT1 high to SSCLK valid
–1*
10
–1
10
ns
9
Delay time, CLKOUT1 high to low group invalid
–1*
10*
–1
10
ns
10
Delay time, CLKOUT1 high to low group valid
–1*
–1
ns
11
Delay time, CLKOUT1 high to high group invalid
–1*
10*
–1
10
ns
12
Delay time, CLKOUT1 high to high group valid
–1*
–1
ns
13
Delay time, CLKOUT1 high to Z group high impedance
–1*
10*
–1
10
ns
14
Delay time, CLKOUT1 high to Z group valid
–1*
–1
ns
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HRDY and HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
*This parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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