參數(shù)資料
型號(hào)： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 34/73頁
文件大小： 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles
(see Figure 13 and Figure 14)
NO.
’C6201-150
MIN
’C6201B-150
MIN
’C6201B-200
MIN
UNIT
MAX
MAX
MAX
6
tsu(EDV-CKO1H)
Setup time, read EDx valid before CLKOUT1
high
5.0
5.0
4.0
ns
7
th(CKO1H-EDV)
tsu(ARDY-CKO1H)
th(CKO1H-ARDY)
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
*This parameter is not production tested.
Hold time, read EDx valid after CLKOUT1 high
0
0
0.8
ns
10
Setup time, ARDY valid before CLKOUT1 high
5.0*
5.0
4.0
ns
11
Hold time, ARDY valid after CLKOUT1 high
0*
0
0.8
ns
switching characteristics for asynchronous memory cycles
(see Figure 13 and Figure 14)
NO.
PARAMETER
’C6201-150
MIN
’C6201B-150
MIN
’C6201B-200
MIN
UNIT
MAX
MAX
MAX
1
td(CKO1H-CEV)
td(CKO1H-BEV)
td(CKO1H-BEIV)
td(CKO1H-EAV)
td(CKO1H-EAIV)
td(CKO1H-AOEV)
td(CKO1H-AREV)
td(CKO1H-EDV)
td(CKO1H-EDIV)
td(CKO1H-AWEV)
Delay time, CLKOUT1 high to CEx valid
–1.0
5.0
–1.0
5.0
–0.2
4.0
ns
2
Delay time, CLKOUT1 high to BEx valid
–1.0
5.0
–1.0
5.0
–0.2
4.0
ns
3
Delay time, CLKOUT1 high to BEx invalid
–1.0*
5.0*
–1.0
5.0
–0.2
4.0
ns
4
Delay time, CLKOUT1 high to EAx valid
–1.0
5.0
–1.0
5.0
–0.2
4.0
ns
5
Delay time, CLKOUT1 high to EAx invalid
–1.0*
5.0*
–1.0
5.0
–0.2
4.0
ns
8
Delay time, CLKOUT1 high to AOE valid
–1.0
5.0
–1.0
5.0
–0.2
4.0
ns
9
Delay time, CLKOUT1 high to ARE valid
–1.0
5.0
–1.0
5.0
–0.2
4.0
ns
12
Delay time, CLKOUT1 high to EDx valid
5.0
5.0
4.0
ns
13
Delay time, CLKOUT1 high to EDx invalid
–1.0*
–1.0
–0.2
ns
14
Delay time, CLKOUT1 high to AWE valid
–1.0
5.0
–1.0
5.0
–0.2
4.0
ns
The minimum delay is also the minimum output hold after CLKOUT1 high.
*This parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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