參數(shù)資料
型號(hào)： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 38/73頁(yè)
文件大?。?/td> 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17) (’C6201)
NO.
’C6201-150
MIN
UNIT
MAX
7
tsu(EDV-SSCLKH)
th(SSCLKH-EDV)
Setup time, read EDx valid before SSCLK high
3.6*
ns
8
Hold time, read EDx valid after SSCLK high
1.2*
ns
*This parameter is not production tested.
switching characteristics for synchronous-burst SRAM cycles
(half-rate SSCLK)
(see Figure 17 and Figure 18) (’C6201)
NO.
PARAMETER
’C6201-150
MIN
UNIT
MAX
1
tsu(CEV-SSCLKH)
toh(SSCLKH-CEV)
tsu(BEV-SSCLKH)
toh(SSCLKH-BEIV)
tsu(EAV-SSCLKH)
toh(SSCLKH-EAIV)
tsu(ADSV-SSCLKH)
toh(SSCLKH-ADSV)
tsu(OEV-SSCLKH)
toh(SSCLKH-OEV)
tsu(EDV-SSCLKH)
toh(SSCLKH-EDIV)
tsu(WEV-SSCLKH)
toh(SSCLKH-WEV)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
*This parameter is not production tested.
Setup time, CEx valid before SSCLK high
P – 4.1*
ns
2
Output hold time, CEx valid after SSCLK high
P – 5.7*
ns
3
Setup time, BEx valid before SSCLK high
P – 4*
ns
4
Output hold time, BEx invalid after SSCLK high
P – 5.7*
ns
5
Setup time, EAx valid before SSCLK high
P – 4*
ns
6
Output hold time, EAx invalid after SSCLK high
P – 5.7*
ns
9
Setup time, SSADS valid before SSCLK high
P – 4*
ns
10
Output hold time, SSADS valid after SSCLK high
P – 5.7*
ns
11
Setup time, SSOE valid before SSCLK high
P – 4*
ns
12
Output hold time, SSOE valid after SSCLK high
P – 5.7*
ns
13
Setup time, EDx valid before SSCLK high
P – 4*
ns
14
Output hold time, EDx invalid after SSCLK high
P – 5.7*
ns
15
Setup time, SSWE valid before SSCLK high
P – 4*
ns
16
Output hold time, SSWE valid after SSCLK high
P – 5.7*
ns
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