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DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
V
CC
V
SS
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
JD PACKAGE
(TOP VIEW)
G
DQ3
V
SS
DQ2
RAS
A0
A2
V
CC
A5
A7
CAS
DQ4
DQ1
W
TF
A1
A3
A4
A6
A8
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
SV PACKAGE
(TOP VIEW)
RAS
TF
A0
A1
A2
A3
V
CC
A8
A7
A6
A5
A4
V
SS
DQ4
DQ3
CAS
G
HJ PACKAGE
(TOP VIEW)
DQ1
DQ2
W
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
FQ/HL PACKAGES
(TOP VIEW)
V
SS
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
V
CC
HK PACKAGE
(TOP VIEW)
RAS
TF
A0
A1
A2
A3
V
CC
A8
A7
A6
A5
A4
V
SS
DQ4
DQ3
CAS
G
DQ1
DQ2
W
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Organization . . . 262144 Words
×
4 Bits
Single 5-V Supply (10% Tolerance)
Processed to MIL-STD-833, Class B
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
ta(R)
(tRAC)
(MAX)
SMJ44C256-80
80 ns
SMJ44C256-10
100 ns
SMJ44C256-12
120 ns
SMJ44C256-15
150 ns
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
Long Refresh Period
512-Cycle Refresh in 8 ms (Max)
All Inputs and Clocks are TTL Compatible
TIME
ta(C)
(tCAC)
(MAX)
20 ns
25 ns
30 ns
40 ns
TIME
ta(CA)
(tCAA)
(MAX)
40 ns
45 ns
55 ns
70 ns
OR
WRITE
CYCLE
(MIN)
150 ns
190 ns
220 ns
260 ns
3-State Unlatched Output
Low Power Dissipation
Packaging Offered:
– 20-Pin 300-Mil Ceramic DIP (JD Suffix)
– 20-Lead Ceramic Surface-Mount Package
(HJ Suffix)
– 20-Pin Ceramic Flat Pack (HK Suffix)
– 20-Terminal Leadless Ceramic
Surface-Mount Package (FQ Suffix)
– 20-Terminal Low-Profile Leadless
Ceramic Surface-Mount Package
(HL Suffix)
– 20-Pin Ceramic Zig Zag In-Line Package
(SV Suffix)
Operating Free-Air Temperature Range
– 55
°
C to 125
°
C
PIN NOMENCLATURE
A0–A8
CAS
DQ1–DQ4
G
RAS
TF
VCC
VSS
W
Address Inputs
Column Address Strobe
Data In/Data Out
Data Output Enable
Row Address Strobe
Test Function
5-V Supply
Ground
Write Enable
Copyright
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.