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| 型號(hào)： | SMJ44C256 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 262144 4位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 323K |
| 代理商： | SMJ44C256 |
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating temperature
(continued) (see Note 5)
PARAMETER
ALT.
’44C256-80
MIN
’44C256-10
MIN
’44C256-12
MIN
’44C256-15
MIN
UNIT
SYMBOL
MAX
MAX
MAX
MAX
td(CARH)
Delay time, column address to
RAS high
tRAL
40
45
55
70
ns
td(CACH)
Delay time, column address to
CAS high
tCAL
40
45
55
70
ns
td(RLWL)
Delay time, RAS low to W low
(see Note 14)
tRWD
130
150
170
200
ns
td(CAWL)
Delay time, column address to W
low (see Note 14)
tAWD
80
95
105
120
ns
td(GHD)
Delay time, G high before data at
DQ
tGDD
20
25
30
40
ns
td(GLRH)
Delay time, G low to RAS high
tGSR
20
25
30
40
ns
td(RLCH)R
Delay time, RAS low to CAS high
(see Note 16)
tCHR
20
25
25
30
ns
td(CLRL)R
Delay time, CAS low to RAS low
(see Note 16)
tCSR
10
10
10
15
ns
td(RHCL)R
Delay time, RAS high to CAS low
(see Note 16)
tRPC
0
0
0
0
ns
trf
tt
Refresh time interval
tREF
tT
8
8
8
8
ms
Transition time (see Note 17)
5. Timing measurements in this table are referenced to VIL max and VIH min.
14. Read-modify-write operation only
16. CBR refresh only
17. System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
ns
NOTES:
PARAMETER MEASUREMENT INFORMATION
1.31 V
Output Under Test
RL = 218
CL = 80 pF
(See Note A)
R1 = 828
CL = 80 pF
(See Note A)
R2 = 295
5 V
Output Under Test
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
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