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| 型號： | SMJ44C256 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 262144 4位動態(tài)隨機(jī)存取存儲器 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 323K |
| 代理商： | SMJ44C256 |
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Valid Out
RAS
CAS
A0–A8
W
DQ1–DQ4
G
Don’t Care
Don’t Care
Column
Row
Column
tw(RL)P
tw(RH)
tc(P)
tw(CL)
td(RLCH)
td(RLCL)
tsu(RA)
th(RA)
td(CACH)
td(CARH)
th(CHrd)
th(RHrd)
ta(CA)
(see Note A)
tdis(CH)
ta(CP)
(see Note C)
See Note A
ta(C)
ta(CA)
ta(R)
ta(G)
tdis(G)
td(RLCA)
tsu(rd)
Valid Out
See Note A
tsu(CA)
th(CA)
th(RLCA)
td(CHRL)
td(CLRH)
tw(CH)
Don’t Care
Don’t Care
tdis(G)
ta(G)
Don’t Care
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write-cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
C. Access time is ta(CP)- or ta(CA)-dependent.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
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