參數(shù)資料
型號(hào): SM320VC33HFGM150
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 75 MHz, OTHER DSP, CQFP164
封裝: NCTB, CERAMIC, MO-113AA, QFP-164
文件頁(yè)數(shù): 44/56頁(yè)
文件大小: 669K
代理商: SM320VC33HFGM150
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following
tables define the timing parameters for the timer pin.
timing requirements for timer pin (see Figure 36 and Figure 37)
MIN
MAX
UNIT
tsu(TCLK-H1L)
Setup time, TCLK external before H1 low
3*
ns
th(H1L-TCLK)
Hold time, TCLK external after H1 low
0
ns
* Not production tested
These requirements are applicable for a synchronous input clock.
switching characteristics over recommended operating conditions for timer pin (see Figure 36 and
Figure 37)
PARAMETER
MIN
MAX
UNIT
td(H1H-TCLK)
Delay time, H1 high to TCLK internal valid
3
ns
t
Cycle time TCLK
TCLK ext
tc(H) x 2.6*
ns
tc(TCLK)
Cycle time, TCLK
TCLK int
tc(H) x 2*
tc(H) x 232*
ns
t
Pulse duration TCLK
TCLK ext
tc(H) + 5*
ns
tw(TCLK)
Pulse duration, TCLK
TCLK int
[tc(TCLK)/2] - 4*
[tc(TCLK)/2] + 4*
ns
* Not production tested
These parameters are applicable for an asynchronous input clock.
TCLK as input
H1
H3
tsu(TCLK-H1L)
th(H1L-TCLK)
tsu(TCLK-H1L)
tw(TCLK)
tc(TCLK)
Figure 36. Timer Pin Timing, Input
TCLK as output
H1
H3
td(H1H-TCLK)
Figure 37. Timer Pin Timing, Output
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