參數(shù)資料
型號: SM320VC33HFGM150
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 75 MHz, OTHER DSP, CQFP164
封裝: NCTB, CERAMIC, MO-113AA, QFP-164
文件頁數(shù): 39/56頁
文件大?。?/td> 669K
代理商: SM320VC33HFGM150
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 30 and Figure 31 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s
Guide (literature number SPRU031).
The serial-port timing parameters are defined in the preceding “serial-port timing parameters” tables. The
numbers shown in Figure 30 and Figure 31 correspond with those in the NO. column of each table.
FSX(EXT)
FSX(INT)
FSR
DR
DX
CLKX/R
H1
Bit 0
Bit n-1
Bit n-2
Bit n-1
Bit n-2
td(H1H-SCK)
tc(SCK)
tw(SCK)
tr(SCK)
tf(SCK)
td(CLKX- DX)
tsu(DR- CLKRL)
th(CLKRL- DR)
td(CLKX- FSX)
tsu(FSR- CLKRL)
td(CLKX- FSX)
th(SCKL- FS)
tsu(FSX- CLKX)
td(CLKX- DX)V
tdis(CLKX- DXZ)
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 30. Fixed Data-Rate Mode Timing
CLKX/R
FSX(INT)
FSX(EXT)
DX
FSR
DR
Bit 0
Bit n-2
Bit n-3
Bit n-2
Bit n-3
Bit n-1
td(CLKX- FSX)
td(FSX- DX)V
tsu(FSX- CLKX)
tsu(DR- CLKRL)
td(CLKX- DX)
th(CLKRL-DR)
th(SCKL-FS)
tsu(FSR-CLKRL)
td(CLKX-DX)V
tdis(CLKX-DXZ)
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 31. Variable Data-Rate Mode Timing
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