參數(shù)資料
型號(hào): SM320VC33HFGM150
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 75 MHz, OTHER DSP, CQFP164
封裝: NCTB, CERAMIC, MO-113AA, QFP-164
文件頁(yè)數(shù): 37/56頁(yè)
文件大小: 669K
代理商: SM320VC33HFGM150
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 29
correspond with those in the NO. column of the table below.
NOTE: The IACK instruction can be executed at anytime to signal an event. It is most often used within an
interrupt routine to signal which interrupt has occurred.
switching characteristics over recommended operating conditions for IACK (see Figure 29)
PARAMETER
MIN
MAX
UNIT
td(H1H-IACKL)
Delay time, H1 high to IACK low
-1*
3
ns
td(H1H-IACKH)
Delay time, H1 high to IACK high
-1*
3
ns
* Not production tested
H3
H1
IACK
ADDR
Data
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
td(H1H-IACKL)
td(H1H-IACKH)
Figure 29. Interrupt Acknowledge (IACK) Timing
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