參數(shù)資料
型號： SM320VC33HFGM150
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CQFP164
封裝： NCTB, CERAMIC, MO-113AA, QFP-164
文件頁數(shù)： 13/56頁
文件大小： 669K
代理商： SM320VC33HFGM150
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
designing a target system emulator connector (14-pin header) (continued)
Although other headers can be used, recommended parts include:
straight header, unshrouded
DuPont Connector Systems
part numbers:
65610-114
65611-1 14
67996-114
67997-114
JTAG emulator cable pod logic
Figure 12 shows a portion of the emulator cable pod. The functional features of the pod are as follows:
D Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By
default, these signals are not terminated.
D Signal TCK is driven with a 74LVT240 device. Because of the high-current drive (32 mA IOL/IOH), this signal
can be parallel-terminated. If TCK is tied to TCK_RET, the parallel terminator in the pod can be used.
D Signals TMS and TDI can be generated from the falling edge of TCK_RET, according to the bus slave device
timing rules.
D Signals TMS and TDI are series-terminated to reduce signal reflections.
D A 10.368-MHz test clock source is provided. Another test clock can be used for greater flexibility.
100
TL7705A
RESIN
270
JP2
180
TCK_RET (Pin 9){
EMU1 (Pin 14)
EMU0 (Pin 13)
74AS1034
GND (Pins 4,6,8,10,12)
TRST (Pin 2)
TCK (Pin 11){
10.368 MHz
33
33
TDI (Pin 3)
TMS (Pin 1)
TDO (Pin 7)
74LVT240
180
JP1
270
74F175
Q
D
PD(VCC) (Pin 5)
+5 V
74AS1004
Y
A
The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system
test clock source.
Figure 12. JTAG Emulator Cable Pod Interface
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