參數(shù)資料
型號(hào)： SM320C6701GJCA16EP
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 166.67 MHz, OTHER DSP, PBGA352
封裝： 35 X 35 MM, PLASTIC, BGA-352
文件頁(yè)數(shù)： 62/62頁(yè)
文件大小： 894K
代理商： SM320C6701GJCA16EP
SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLOCK/PLL
CLKIN
C10
I
Clock Input
CLKOUT1
AF22
O
Clock output at full device speed
CLKOUT2
AF20
O
Clock output at half of device speed
CLKMODE1
C6
I
Clock mode select
CLKMODE0
C5
I
Selects whether the output clock frequency = input clock frequency x4 or x1
PLLFREQ3
A9
PLL frequency range (3, 2, and 1)
PLLFREQ2
D11
I
PLL frequency range (3, 2, and 1)
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
PLLFREQ1
B10
I
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
PLLV
D12
A§
PLL analog VCC connection for the low-pass filter
PLLG
C12
A§
PLL analog GND connection for the low-pass filter
PLLF
A11
A§
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
L3
I
JTAG test-port mode select (features an internal pullup)
TDO
W2
O/Z
JTAG test-port data out
TDI
R4
I
JTAG test-port data in (features an internal pullup)
TCK
R3
I
JTAG test-port clock
TRST
T1
I
JTAG test-port reset (features an internal pulldown)
EMU1
Y1
I/O/Z
Emulation pin 1, pullup with a dedicated 20-k
resistor
EMU0
W3
I/O/Z
Emulation pin 0, pullup with a dedicated 20-k
resistor
CONTROL
RESET
K2
I
Device reset
NMI
L2
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
U3
EXT_INT6
V2
I
External interrupts
EXT_INT5
W1
I
External interrupts
Edge-driven (rising edge)
EXT_INT4
U4
Edge-driven (rising edge)
IACK
Y2
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
AA1
Active interrupt identification number
INUM2
W4
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
INUM1
AA2
O
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
INUM0
AB1
Encoding order follows the interrupt-service fetch-packet ordering
LENDIAN
H3
I
If high, LENDIAN selects little-endian byte/half-word addressing order within a word
If low, LENDIAN selects big-endian addressing
PD
D3
O
Power-down mode 3 (active if high)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these
pins.
§ A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
相關(guān)PDF資料
PDF描述
SM320C6701GLPW16 32-BIT, 167 MHz, OTHER DSP, CBGA429
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SM320C6701GLPS16 制造商:Texas Instruments 功能描述:DSP,1000 MFLOPS,167MHZ,-40C/+90C,C-BGA - Trays
SM320C6701GLPW14 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 140MHz 1120MIPS 429-Pin CFCBGA Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TISSM320C6701GLPW14 FLOATING POINT DSP
SM320C6701S14 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SM320C6701S16 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SM320C6701W14 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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