參數(shù)資料
型號(hào)： SM320C6701GJCA16EP
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 166.67 MHz, OTHER DSP, PBGA352
封裝： 35 X 35 MM, PLASTIC, BGA-352
文件頁(yè)數(shù)： 36/62頁(yè)
文件大?。?/td> 894K
代理商： SM320C6701GJCA16EP
SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD/HOLDA TIMING
timing requirements for the hold/hold acknowledge cycles (see Figure 24)
NO.
C6701-120
C6701-167
UNIT
NO.
MIN
MAX
UNIT
1
tsu(HOLDH-CKO1H)
Setup time, HOLD high before CLKOUT1 high
5
ns
2
th(CKO1H-HOLDL)
Hold time, HOLD low after CLKOUT1 high
2
ns
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
switching characteristics for the hold/hold acknowledge cycles (see Figure 24)
NO.
PARAMETER
C6701-120
C6701-167
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
3
tR(HOLDL-EMHZ)
Response time, HOLD low to EMIF high impedance
4P
§
ns
4
tR(EMHZ-HOLDAL)
Response time, EMIF high impedance to HOLDA low
2P
ns
5
tR(HOLDH-HOLDAH)
Response time, HOLD high to HOLDA high
4P
7P
ns
6
td(CKO1H-HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
1
8
ns
7
td(CKO1H-BHZ)
Delay time, CLKOUT1 high to EMIF Bus high impedance
1
8
ns
8
td(CKO1H-BLZ)
Delay time, CLKOUT1 high to EMIF Bus low impedance
1
12
ns
9
tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance
3P
6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus
External Requester
DSP Owns Bus
’C6701
Ext Req
’C6701
8
7
3
4
6
1
2
CLKOUT1
HOLD
HOLDA
EMIF Bus
1
5
9
2
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
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