SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Table of Contents
parameter measurement information
. . . . . . . . . . . . . . .
signal-transition levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
input and output clocks
. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing
. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing
. . . . . . . . . . . . . . . . .
synchronous DRAM timing
. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing
. . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing
. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing
. . . . . . . . . . . . .
DMAC, timer, power-down timing
. . . . . . . . . . . . . . . . . .
JTAG test-port timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU diagram
. . . . . . . . . . . . . . . . . . . . .
CPU description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal groups description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
. . . . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature
. . . .
description
The 320C67x DSPs are the floating-point DSP
family in the TMS320C6000
DSP platform. The
SM320C6701-EP and SM320C6701MECH-EP
(C6701) devices are based on the high-
performance,
advanced
VelociTI
very-long-
instruction-word (VLIW) architecture developed
by Texas Instruments (TI), making this DSP an
excellent
choice
for
multichannel
and
multifunction applications. With performance of
up to 1 giga floating-point operations per second
(GFLOPS) at a clock rate of 167 MHz, the C6701
offers
cost-effective
solutions
to
high-
performance DSP programming challenges. The
C6701 DSP possesses the operational flexibility
of high-speed controllers and the numerical
capability of array processors. This processor has
32 general-purpose registers of 32-bit word length
and eight highly independent functional units. The
eight functional units provide four floating-/fixed-
point ALUs, two fixed-point ALUs, and two
floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total
of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic,
on-chip memory, and additional on-chip peripherals.
The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
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