SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description (continued)
The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows
debugger interface for visibility into source code
execution.
mechanical shock-tolerant package option
Typically, industry-standard non-hermetic plastic ball grid array (PBGA) packages manufactured with a metal
heat spreader/lid for die coverage are not designed to be tolerant of high levels of mechanical shock. For
systems that experience significant mechanical shock, additional board/module design effort is required to allow
for the use of the typical PBGA. Therefore, TI designed the Mech~Shock package for selected C6000 platform
DSPs for use in applications that will encounter high levels of mechanical shock (e.g., missiles and self-guided
projectiles/munitions). The Mech~Shock package is a mechanical-shock package embodiment qualified to
20,000 Gs of mechanical shock. Qualification testing is per MIL-STD-883E, Method 2002.3, Test Condition F.
The Mech~Shock package, while non-hermetic, directly addresses the shock stress-environments of system
applications that experience severe shock profiles during operation. Mech~Shock packages incorporate a
composite (and lighter) heat spreader/lid. The composite heat spreader has equivalent thermal performance
to the heavier, solid copper heat spreaders, but the composite lid is less massive. This composite lid is placed
on a standard-footprint PBGA substrate and attached with adhesives that have unique, shock-tolerant
characteristics. A Mech~Shock package is footprint compatible with the standard commercial package for the
same DSP product.
device characteristics
Table 1 provides an overview of the C6701 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc.
Table 1. Characteristics of the C6701 Processors
HARDWARE FEATURES
C6701
EMIF
1
DMA
4-Channel
Peripherals
Host-Port Interface (HPI)
1
Peripherals
McBSPs
2
32-Bit Timers
2
Internal Program Memory
Size (Bytes)
64K
Internal Program Memory
Organization
64K Bytes Cache/Mapped Program
Internal Data Memory
Size (Bytes)
64K
Internal Data Memory
Organization
2 Blocks: Eight 16-Bit Banks per Block 50/50 Split
Frequency
MHz
120, 167
Cycle Time
ns
6 ns (6701-167); 8.3 ns (6701-120)
Core (V)
1.8 (6701-120)
Voltage
Core (V)
1.9 (6701-167)
Voltage
I/O (V)
3.3
PLL Options
CLKIN frequency multiplier
Bypass (x1), x4
BGA Package
35 x 35 mm
352-pin GJC
Process Technology
m
0.18
m
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD