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參數(shù)資料
| 型號： | SDA9206 |
| 廠商： | SIEMENS A G |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | ADC with Built in Antialiasing filter and Clock generation UnitS |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大?。?/td> | 255K |
| 代理商： | SDA9206 |
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SDA 9206
Semiconductor Group
42
1999-02-10
2.4.5
Status Byte 0
Read Mode
Bit
D7
Name
CON
Function
Absolute difference between the horizontal sync pulse in SYNC
and the HPLL:
0:
Larger than or equal to 32 system clock cycles
1:
Less than 32 system clock cycles
THRELIM Absolute difference between the horizontal sync pulse in SYNC
and the HPLL:
0:
Larger than 8 system clock cycles
1:
Less than 8 system clock cycles for 8 or more
successive lines (i.e. HPLL well locked in)
FFGF, FF Identified number
of lines per field
(refer also to timing diagram
figure 16
):
< N1
≥
N1 and
≤
N2
> N2 and < 287
≥
287 and < N3
≥
N3 and
≤
N4
> N4
N1 to N4 depends on Control Bits VWIWI:
VWIWI1
VWIWI0
N1
0
0
262
0
1
250
1
0
240
1
1
200
don′t care
POR
Status bit POR is set by power on reset or by activating the reset pin.
POR is reset after reading the status byte.
D6
D5, D4
Status Bits
FFGF
FF
0
1
0
0
1
0
0
0
0
1
1
1
N2
264
275
285
312
N3
312
300
290
250
N4
314
325
335
362
D3
D2 ... D0
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