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參數(shù)資料
| 型號： | SDA9206 |
| 廠商： | SIEMENS A G |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | ADC with Built in Antialiasing filter and Clock generation UnitS |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 255K |
| 代理商： | SDA9206 |
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SDA 9206
Semiconductor Group
22
1999-02-10
to adapt the nominal frequency of the DTO by means of 5
I
2
C-Bus bits (INC4...INC0)
such shifting the center frequency according to the momentary standard used.
For the different applications the following values of INC are allowed (values valid for
a crystal frequency of 24.576 MHz):
Note:
A change of INC causes spontaneous changes of the generated clock
frequencies!
The DTO generates a saw-tooth with a frequency that is proportional to the increment.
The saw-tooth is converted into a sinusoidal clock signal by means of a D/A converter
and applied to an analog PLL which multiplies the frequency and minimizes residual
jitter.
By means of the
I
2
C bits S1CL and S2CL the output frequency on pins CLK1 and CLK2
can be set. In this manner a clock is provided that is line-locked with the SYNC-input
signal. The ratio of these clock frequencies to the horizontal frequency of SYNC depends
only on the
I
2
C-Bus bits S1CL, S2CL, HPLL and 2FH.
For the different modes the following values of S1CL and S2CL are allowed:
The digital horizontal PLL supplies a noise-suppressed horizontal pulse.
Application
PAL
NTSC
PAL (100 Hz/VGA)
NTSC (120 Hz/VGA) 31500
ATV
MUSE
Macintosh
VGA
FH [Hz]
15625
15750
31250
2FH
0
0
1
1
1
1
1
1
YUV-ADCs
active
active
inactive
inactive
inactive
inactive
inactive
inactive
INC
6
6
6
6
8
11
14
21
32400
33750
35000
38000
Mode
YUV-ADC
2FH
S1CL
S2CL
f
CLK1
(MHz)
27
27
27
13.5
6.25 ... 8.75 25 ... 35
12.5 ... 17.5 25 ... 35
f
CLK2
(MHz)
27
tristate
27
tristate
CCIR
CCIR
4:2:2, 4:1:1 enabled
4:2:2, 4:1:1 enabled
VGA
VGA
enabled
enabled
0
0
0
0
1
1
11
11
11
10
01
10
11
00
11
00
11
11
disabled
disabled
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