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參數(shù)資料
| 型號： | SDA9206 |
| 廠商： | SIEMENS A G |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | ADC with Built in Antialiasing filter and Clock generation UnitS |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 21/54頁 |
| 文件大?。?/td> | 255K |
| 代理商： | SDA9206 |
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SDA 9206
Semiconductor Group
21
1999-02-10
Table 2
Output Coding in Case of CCIR 656 Format, FORMAT = 00
V
CY
,
V
CU,V
: ext. clamping level during clamping at
C
ext cl
on channel AINY
resp. AINU, AINV
Table 2
is valid for
V
REFL
= 2.2 V and
V
REFH
= 4.2 V, xAMP = 0000
2.3
The clock sync generator is a phase locked loop that locks on a horizontal SYNC input
signal and generates the clock signals as well as additional control output signals.
Clock Sync Generation
2.3.1
The input signal SYNC may be either a CVBS signal or a composite sync signal. The
polarity of the SYNC signal can be both positive or negative (
I
2
C-Bit SYPOL). The edges
of the SYNC input pulses should not be steeper than 100 ns. The frequency of the SYNC
signal can be of normal or double line frequency (
I
2
C-Bit 2FH).
The SYNC is clamped before A/D conversion. For DC-input signals clamping can be
disabled (
I
2
C-Bit CLOF). A/D conversion takes place with 7 bits and a nominal frequency
of 27 MHz.
The digital HPLL filters the signal with a cutoff frequency of 1 MHz (2 MHz for 2fh mode).
If 1fh mode is used the sampling frequency is decimated to 13.5 MHz. Following the low
pass filtering a black- and sync bottom- level measurement takes place in order to
calculate a threshold value. By means of this value the phase difference between the
HPLL output and the SYNC input pulse is determined. Using a digital PI filter an
increment is calculated from this for the Discrete Timing Oscillator (DTO). It is possible
Horizontal PLL (HPLL)
Step
AINY
AINU, AINV
OFL
Bit
UFL
Bit
Straight
Binary
7654 3210
0000 0001
0000 0001
0000 0001
0000 0010
1111 1101
1111 1110
1111 1110
1111 1110
Two’s
Complement
7654 3210
1000 0000
1000 0000
1000 0001
1000 0010
0111 1101
0111 1110
0111 1111
0111 1111
Underflow
0
1
2
253
254
255
Overflow
<
V
CY
- 0.125 V
V
CY
- 0.125 V
V
CY
- 0.117 V
V
CY
- 0.109 V
V
CY
+ 1.859 V
V
CY
+ 1.867 V
V
CY
+ 1.875 V
>
V
CY
+ 1.875 V
<
V
CU, V
- 1.0 V
V
CU, V
- 1.0 V
V
CU, V
- 0.992 V
V
CU, V
- 0.984 V
V
CU, V
+ 0.984 V
V
CU, V
+ 0.992 V
V
CU, V
+ 1.0 V
>
V
CU, V
+ 1.0 V
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
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