參數(shù)資料
型號(hào): SAF82526
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 46/126頁
文件大?。?/td> 730K
代理商: SAF82526
Semiconductor Group
46
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The circuit mentioned above results in a slower data transfer with the HSCX. HSCX usually
performs block transfers. The block length is up to 32 bytes. The DMA request line of the IC
remains active as long as more data are needed. Having transmitted the last byte the DMA
request is being reset. Using the additional circuit the DMA request line will be active at least
shortly before T4. So the next DMA cycle will be started four (instead of two) clock cycles later.
Therefore the maximum transmission rate is reduced from 1.25 Mbyte/s to 1.04 Mbyte/s (clock
rate: 12.5 MHz).
For more information refer to
chapter 7.2
(Data Transmission: DMA Mode),
chapter
7.3
(Data
Reception: DMA mode), and Appendix C (Application Example HSCX with 80(C)188 using
DMA).
ITD02700
T1
T2
T3
T4
T1
T2
T3
T4
t
DRHSYS
t
CLCSV
t
CHCSX
CLOCKOUT
DRQTx
RD
(Memory)
CS
(FIFO)
WR
(FIFO)
t
DRHSYS
max
= T2 + T3
f
CLKOUT
- t
CVCTV
+ t
CHCSX
t
CVCTV
t
CLCL
t
CHCSX
t
DRHSYS
max
8 MHz
12.5
MHz
16
125 ns
ns
80
62.5
56 ns
47
ns
31
5 ns
ns
5
ns
5
261ns
158
130
ns
ns
ns
MHz
ns
T4/2
+
DRQ
CVCTV
t
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