參數(shù)資料
型號: SAF82526
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數(shù)據(jù)通信集成電路
文件頁數(shù): 45/126頁
文件大小: 730K
代理商: SAF82526
Semiconductor Group
45
SAB 82525
SAB 82526
SAF 82525
SAF 82526
If you use the write signal instead of the chip select signal in order to reset the DMA request
you gain some time. The extra circuit is just an AND gate. The first input of the AND gate is
connected to the DMA request line of the peripheral IC; the second input is connected to the
chip select line. The AND gate’s output is the DMA request signal for the 80(C)188.
Theoretically, the request line of an 80(C)188, for example, would still be active when the de-
termination is made and DMA cycles would be performed permanently. Therefore the decision
of the DMA request line is delayed; it is already made two clock cycles before the end of the
write cycle. If no wait-states are inserted the decision is made at the end of the T2 clock cycle.
Due to the fact that the write signal will be valid at the beginning of T2 there is only little time
left for resetting the DMA request line.
ITD02698
T1
T2
T3
T4
T1
T2
T3
T4
t
DRHSYS
t
CVCTV
t
INVCL
CLOCKOUT
DRQ
RD
(Memory)
WR
(FIFO)
t
DRHSYS
max
= T2 - t
CVCTV
-t
INVCL
f
CLKOUT
t
CLCL
t
CVCTV
t
INVCL
t
DRHSYS
max
8 MHz
12.5
MHz
16
125 ns
ns
80
62.5
56 ns
47
ns
31
15 ns
15
15
54 ns
18
16.5
ns
ns
ns
ns
MHz
ns
ns
ITS02699
&
DRQ
PCS
80(C)188
HSCX
DRQTx
CS
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