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參數(shù)資料
| 型號(hào)： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁(yè)數(shù)： | 8/76頁(yè) |
| 文件大小： | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
8
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7
FUNCTIONAL DESCRIPTION
7.1
Microprocessor interfaces
The SAA7392 is programmed via two independent
microprocessor interfaces:
Serial I
2
C-bus
– SDA = I
2
C-bus data
– SCL = I
2
C-bus clock
– I
2
C-bus write address = 3EH
– I
2
C-bus read address = 3FH.
Parallel 80C51 compatible
– DA(7:0) = address/data bus
– ALE = address latch enable; latches the address
information on the bus
– WRi = active LOW write signal; write to SAA7392
– RDi = active LOW read signal; read from SAA7392
– CSi = chip select signal; gates the RDi and WRi
signals.
7.1.1
S
ERIAL
I
2
C-
BUS INTERFACE
Data is transferred over the interface in single bytes, via
write data or read data commands.
The sequence for a write data command is as follows:
1.
Send START condition
2.
Send address 3EH (write)
3.
Write register address byte
4.
Write data byte
5.
Send STOP condition.
The sequence for a read data command is as follows:
1.
Send START condition
2.
Send address 3EH (write)
3.
Write status register address byte
4.
Send STOP condition
5.
Send address 3FH (read)
6.
Read data byte
7.
Send STOP condition.
7.1.2
P
ARALLEL INTERFACE
The parallel interface has a multiplexed address/data bus.
Information can be written to or read from the SAA7392
using the protocols shown in Figs 3 and 4; specific timings
are shown in Table 2. Note that only the lower six address
bits are decoded; so writing to address 40H would have
the same effect as writing to address 00H.
handbook, full pagewidth
MGR793
ALE
WRi
CSi
DA0 to DA7
address (0:7)
IN
data (0:7)
IN
td1
tWRiL
th1
td2
tsu2
tsu1
th2
Fig.3 Microprocessor write protocol.
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