參數(shù)資料
型號: SAA7392HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Channel encoder/decoder CDR60
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù): 54/76頁
文件大?。?/td> 246K
代理商: SAA7392HL
2000 Mar 21
54
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.16
The EFM clock generator
The EFM clock generator will produce the recording clock based on one of three reference sources. There are five stages
to the function. The first selects the reference source using a multiplexer. The next stage is a digital PLL to up-multiply
the reference source. The source will determine the base frequency output by the PLL, whilst a position error signal is
used to alter the frequency so that the position error tends to zero. Next, an analog PLL is used to up-multiply the output
from the digital PLL. The output of the analog PLL is then multiplexed with an external source to allow the EFM clock
generator to be bypassed completely. Finally, a programmable divider is used to enable the clock output, XEFM, to be
doubled producing XEFM_2.
handbook, full pagewidth
MGR808
DIGITAL
PLL
MUX
W441
WCLK
Sysclk/192
MUX
XError
Fifo filling
Sysclk
Config Data
MUX
XEFM
PROGRAMMABLE
DIVIDER
ANALOG
PLL
+
Kp
Ki
+
INTEGRATOR
Fig.18 EFM PLL block diagram.
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