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參數(shù)資料
| 型號： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 18/76頁 |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
18
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.4
HF analog front-end
The HF ADC in the SAA7392 encodes the EFM high
frequency signal from the disc light pen assembly. These
signals are pre-processed, externally to the SAA7392, by
either AEGER-2 or a DALAS equivalent. The dynamic
range of the ADC is optimized by the inclusion of an
AC coupled AGC function under digital control.
In order to make use of the whole digital front-end
resolution, the output of the gain control amplifier should
constantly deliver 1.4 V
(p-p)
output signal. The gain range
oftheADCisapproximately14 dB,with32 steps.Thegain
control for the variable gain amplifier is controlled by an
on-chip digital gain control block (AGC). This block allows
for both automatic and microprocessor gain control. The
gain control block will detect ADC extreme conditions
(00H or FFH outputs); on these values the gain control
block will decrement the gain. If no extreme codes occur
the gain is incremented.
7.4.1
F
IXED GAIN
Control of the gain is as follows:
1.
Writing XX1X XXXX to the Anaset1 register
(address 15H) increases the AGC gain by 1.1 dB
2.
Writing XX0X XXXX to the AnaSet1 register
(address 15H) decreases the AGC gain by 1.1 dB
3.
Instructions to increment/decrement gain are ignored
when the AGC gain limits of
4/+12 dB are reached.
7.4.2
A
UTOMATIC
G
AIN
C
ONTROL
(AGC)
The gain of the AGC cell is adjusted until the analog signal
at the ADC input extends over the complete range of
the ADC. Detection of this condition is in the digital domain
where the maximum and minimum ADC codes are
measured. The dynamics of the AGC system are as
follows.
1.
If the ADC output codes are not full scale (i.e.
000 0000 and 111 11111) the AGC gain is
incremented in 1.1 dB steps with a time constant of
1000/n
μ
s, where n is the over-speed factor i.e. n = 1
for basic audio CD.
2.
When full scale is detected at the output of the ADC
the AGC gain is fixed provided that full scale is
maintained and clipping does not occur for greater
than 20% of the time.
3.
If clipping occurs for more than 20% of the time, then
the AGC gain is reduced in 1.1 dB steps with a time
constant of 60/n
μ
s.
The ADC and AGC electrical characteristics are specified
in Chapter 9.
7.4.3
A
NALOG
S
ETTINGS
R
EGISTER
1 (A
NA
S
ET
1)
Table 21
Analog Settings Register 1 (address 15H) - WRITE
Table 22
Description of AnaSet1 bits
7
6
5
4
3
2
1
0
GainControl
MaxGain
StepUp
StepDown
PowerDown
BIT
SYMBOL
DESCRIPTION
7
GainControl
If GainControl = 0, then gain control is in Hold mode. If GainControl = 1, then automatic
gain control is on.
If MaxGain = 0, then there is no gain limit. If MaxGain = 1, then the maximum gain is
7.66 dB.
If StepUp = 1, then step up gain by one LSB.
If StepDown = 1, then step down gain by one LSB.
If PowerDown = 0, then analog blocks are powered up. If PowerDown = 1, then analog
blocks are powered down.
These 3 bits are reserved and must be set to a logic 0s.
6
MaxGain
5
4
3
StepUp
StepDown
PowerDown
2 to 0
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