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參數(shù)資料
| 型號： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 17/76頁 |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
17
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.3.1
C
LOCK
P
RESET
R
EGISTER
(C
LOCK
P
RE
)
Table 17
Clock Preset Register (address 12H) - WRITE
Table 18
Description of ClockPre bits
Table 19
Selection of system clock frequency
Table 20
Selection of BCLK frequency
7
6
5
4
3
2
1
0
CL1Div
GateBClk
Div.1
Div.0
Mux2
Div2.2
Div2.1
Div2.0
BIT
SYMBOL
DESCRIPTION
7
CL1Div
If CL1Div = 0, then CL1 output frequency is
1
3
f
clk
. If CL1Div = 1, then CL1 output
frequency is
1
2
f
clk
.
If GateBClk = 0, then I
2
S output bit clock gating is disabled. If GateBClk = 1, then I
2
S
output bit clock gating enabled, BCLK is output, clock is automatically stopped if FIFO
underflows (this is known as Flow control mode).
These 2 bits select the system clock frequency (f
clk
); see Table 19. This frequency
should be programmed for the expected disc channel rate (e.g. 4.33 MHz for 1
×
CD)
within the following constraints:
6
GateBClk
5
4
Div.1
Div.0
In this clock range, reliable bit detection is possible. All data found will be written to the
FIFO. It is the responsibility of the user to select system clock values so that the FIFO
performance is controlled.
If Mux2 = 0, then N (bit clock divider pre-scaler) = 1. If Mux2 = 1, then N = M.
These 3 bits select the BCLK frequency (f
BCLK
); see Table 20. It is the responsibility of
the user to select BCLK values so that the FIFO performance is controlled.
3
Mux2
Div2<2:0>
2 to 0
Div.1
Div.0
SYSTEM CLOCK FREQUENCY (f
clk
)
0
0
1
1
0
1
0
1
M
×
f
XTLI
0.5
×
M
×
f
XTLI
0.25
×
M
×
f
XTLI
0.125
×
M
×
f
XTLI
Div2.1
Div2.1
Div2.0
BCLK FREQUENCY (f
BCLK
)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
N
×
f
XTLI
N
×
f
XTLI
1
/
2
(N
×
f
XTLI
)
1
/
3
(N
×
f
XTLI
)
1
/
4
(N
×
f
XTLI
)
1
/
6
(N
×
f
XTLI
)
1
/
8
(N
×
f
XTLI
)
1
/
12
(N
×
f
XTLI
)
Chan2
f
clk
4
Channel rate
×
<
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