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參數(shù)資料
| 型號： | S75PL127JCEBFWU0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Power supply woltage of 2.7 to 3.1 volt |
| 中文描述： | 功率2月7號至三月一日伏的電源woltage |
| 文件頁數(shù)： | 51/183頁 |
| 文件大?。?/td> | 1409K |
| 代理商： | S75PL127JCEBFWU0 |
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52
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
P r e l i m i n a r y
Write Operation Status
The device provides several bits to determine the status of a program or erase opera-
tion: DQ2, DQ3, DQ5, DQ6, and DQ7.
Table 15
and the following subsections describe
the function of these bits. DQ7 and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-
gram or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence.
PPB Status
All PPB Erase (Notes
5
,
6, 13, 14)
PPB Lock Bit Set
PPB Lock Bit Status
(Note 15)
DYB Write (Note 7)
DYB Erase (Note 7)
DYB Status (Note 6)
PPMLB Program (Notes
5
,
6
,
12
)
PPMLB Status (Note 5)
SPMLB Program (Notes
5
,
6
,
12
)
SPMLB Status (Note 5)
4
555
AA
2AA
55
555
90
(SA)WP
RD(0)
6
555
AA
2AA
55
555
60
WP
60
(SA)
40
(SA)WP
RD(0)
3
555
AA
2AA
55
555
78
4
555
AA
2AA
55
555
58
SA
RD(1)
4
4
4
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
48
48
58
SA
SA
SA
X1
X0
RD(0)
6
555
AA
2AA
55
555
60
PL
68
PL
48
PL
RD(0)
5
555
AA
2AA
55
555
60
PL
48
PL
RD(0)
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
RD(0)
5
555
AA
2AA
55
555
60
SL
48
SL
RD(0)
Table 14. Sector Protection Command Definitions
Legend:
DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is
(00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address
bits Amax:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is
(00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1.
2.
3.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are
write operations.
During unlock and command cycles, when lower address bits
are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than
DQ7 are don’t cares.
The reset command returns device to reading array.
Cycle 4 programs the addressed locking bit. Cycles 5 and 6
validate bit has been fully programmed when DQ0 = 1. If
DQ0 = 0 in cycle 6, program command must be issued and
verified again.
Data is latched on the rising edge of WE#.
Entire command sequence must be entered for each portion
of password.
4.
5.
6.
7.
8.
9.
10. The password is written over four consecutive cycles, at
addresses 0-3.
11. A 2 μs timeout is required between any two portions of
password.
12. A 100 μs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have
been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6,
erase command must be issued and verified again. Before
issuing erase command, all PPBs should be programmed to
prevent PPB overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
Command sequence returns FFh if PPMLB is set.
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