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參數(shù)資料
| 型號： | S75PL127JCEBFWU0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Power supply woltage of 2.7 to 3.1 volt |
| 中文描述： | 功率2月7號至三月一日伏的電源woltage |
| 文件頁數(shù)： | 121/183頁 |
| 文件大?。?/td> | 1409K |
| 代理商： | S75PL127JCEBFWU0 |
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122
S29GLxxxN MirrorBit
TM
Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e I n f o r m a t i o n
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using V
ID
. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in
“Ad-
vanced Sector Protection” section on page 115
. Note that if WP#/ACC is at V
IL
when the device is in the standby mode, the maximum input load current is in-
creased. See the table in
“DC Characteristics” section on page 151
.
If the system asserts V
IH
on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or un-
protected using the method described in “Sector Group Protection and
Unprotection”.
Note that W P# has an internal pullup; w hen uncon-
nected, W P# is at V
I H
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to
Table 12
for com-
mand definitions). In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and power-down transitions,
or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This pro-
tects data during V
CC
power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# =
V
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
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