參數(shù)資料
型號(hào)： S29GL128P11FFIR12
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述： 128M X 1 FLASH 3V PROM, 110 ns, PBGA64
封裝： 13 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-64
文件頁(yè)數(shù)： 35/77頁(yè)
文件大?。?/td> 2121K
代理商： S29GL128P11FFIR12
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
Flash Family
35
D a t a
S h e e t
( P r e l i m i n a r y )
7.7.7
Accelerated Program
Accelerated single word programming and write buffer programming operations are enabled through the
WP#/ACC pin. This method is faster than the standard program command sequences.
Note
The accelerated program functions must not be used more than 10 times per sector.
If the system asserts V
HH
on this input, the device automatically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the input to reduce the time required for program operations. The
system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note
that if a “Write-to-Buffer-Abort Reset” is required while in Unlock Bypass mode, the full 3-cycle RESET
command sequence must be used to reset the device. Removing V
HH
from the ACC input, upon completion
of the embedded program operation, returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC to V
HH
.
The WP#/ACC pin must not be at V
HH
for operations other than accelerated programming, or device
damage may result.
It is recommended that WP#/ACC apply V
HH
after power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from V
HH
to V
IH
/V
IL
before powering down V
CC
/V
IO
.
7.7.8
Unlock Bypass
This device features an Unlock Bypass mode to facilitate shorter programming commands. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal
four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. The
Command Definitions
on page 67
shows the requirements for
the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Program, Write Buffer Programming, Write-to-Buffer-Abort
Reset, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must
issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the sector address
and the data 90h. The second cycle need only contain the data 00h. The sector then returns to the read
mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions.
Refer to the
Spansion Low Level Driver User’s Guide
(available soon on
www.spansion.com
) for general
information on Spansion Flash memory software development guidelines.
/* Example: Unlock Bypass Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0020; /* write unlock bypass command */
/* At this point, programming only takes two write cycles. */
/* Once you enter Unlock Bypass Mode, do a series of like */
/* operations (programming or sector erase) and then exit */
/* Unlock Bypass Mode before beginning a different type of */
/* operations. */
Table 7.14
Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Entry Command
Write
Base + 555h
0020h
相關(guān)PDF資料
PDF描述
S29GL128P11FFIV10 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
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