參數(shù)資料
型號(hào)： S25FL001D0FNFI001
廠(chǎng)商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
中文描述： 1M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 6 X 5 MM, LEAD FREE, WSON-8
文件頁(yè)數(shù)： 15/38頁(yè)
文件大小： 488K
代理商： S25FL001D0FNFI001
June 9, 2004 30167A+1
S25FL Family (Serial Peripheral Interface)
15
P r e l i m i n a r y I n f o r m a t i o n
sending a new instruction to the device. It is also possible to read the Status Reg-
ister continuously, as shown in
Figure 6
.
Figure 6. Read Status Register (RDSR) Instruction Sequence
Figure 7. Status Register Format
The status and control bits of the Status Register are as follows:
SRWD bit:
The Status Register Write Disable (SRWD) bit is operated in conjunc-
tion with the Write Protect (W#) signal. The Status Register Write Disable
(SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hard-
ware Protected mode (when the Status Register Write Disable (SRWD) bit is set
to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write
Status Register (WRSR) instruction is no longer accepted for execution.
BP1, BP0 bits:
The Block Protect (BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instruc-
tions. These bits are written with the Write Status Register (WRSR) instruction.
When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant
memory area (as defined in Table
1
and Table
2
) becomes protected against Page
Program (PP), and Sector Erase (SE) instructions. The Block Protect (BP1, BP0)
bits can be written provided that the Hardware Protected mode has not been set.
The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1,
BP0) bits are 0.
WEL bit:
The Write Enable Latch (WEL) bit indicates the status of the internal
Write Enable Latch. When set to 1, the internal Write Enable Latch is set; when
set to 0, the internal Write Enable Latch is reset and no Write Status Register, Pro-
gram or Erase instruction is accepted.
Instruction
High Impedance
MSB
MSB
Status Register Out
Status Register Out
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7 6
5
4
3
2
1 0
7
6
5 4
3
2
1
0
7
SO
SI
SCK
CS#
Status Register Write Disable
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
SRWD
0
0
BP1
BP0
WEL
WIP
b7
b0
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參數(shù)描述
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