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參數(shù)資料
| 型號(hào)： | S1C6P466D0A0A00 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC140 |
| 封裝： | DIE-140 |
| 文件頁(yè)數(shù)： | 156/174頁(yè) |
| 文件大?。?/td> | 1582K |
| 代理商： | S1C6P466D0A0A00 |
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72
EPSON
S1C6P466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11.2 Mask option
(1) Terminal specification
Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the
terminal specification of the I/O port is also applied to the serial interface.
In the S1C6P466, the I/O port specification is fixed at "with pull-up resistor" and "complementary
output".
Therefore, the output specification of the terminals SOUT, SCLK (in master mode) and SRDY (in slave
mode) that are used as output in the input/output port of the serial interface is fixed at complemen-
tary output.
Furthermore, a pull-up resistor is provided for the SIN terminal and the SCLK terminal (in slave
mode) that are used as input terminals.
(2) Polarity of synchronous clock and ready signal
Polarity of the synchronous clock and the ready signal that is output in the slave mode is fixed at
negative polarity (active low).
4.11.3 Master mode and slave mode of serial interface
The serial interface of the S1C6P466 has two types of operation mode: master mode and slave mode.
The master mode uses an internal clock as the synchronous clock for the built-in shift register, and
outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK (P12) terminal and it is used as the synchronous clock for the built-in shift register.
The master mode and slave mode are selected by writing data to the SCS1 and SCS0 registers.
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.11.3.1.
Table 4.11.3.1 Synchronous clock selection
SCS1
1
0
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer
External clock
The maximum clock is limited to 1 MHz.
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the program-
mable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8-bit serial data, is controlled as
follows:
In the master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automati-
cally suspended and the SCLK (P12) terminal is fixed at high level.
In the slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are
masked.
A sample basic serial input/output portion connection is shown in Figure 4.11.3.1.
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