參數(shù)資料
型號: S1C63466D
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC140
封裝: DIE-140
文件頁數(shù): 60/135頁
文件大?。?/td> 1053K
代理商: S1C63466D
22
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer)
4.2 Watchdog Timer
4.2.1 Configuration of watchdog timer
The S1C63466 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as
the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the
software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog
timer is not reset in at least 3–4 seconds, it generates a non-maskable interrupt (NMI) to the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
Watchdog timer
Non-maskable
interrupt (NMI)
OSC1 dividing signal 256 Hz
Watchdog timer enable signal
Watchdog timer reset signal
Fig. 4.2.1.1 Watchdog timer block diagram
The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the
last stage of the counter (0.25 Hz) overflows.
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If a HALT status continues for 3–4 seconds, the non-
maskable interrupt releases the HALT status.
4.2.2 Interrupt function
If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core
CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag =
"0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a
pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is
assigned to 0100H in the program memory.
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