參數(shù)資料
型號(hào): S1C63466D
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC140
封裝: DIE-140
文件頁(yè)數(shù): 126/135頁(yè)
文件大?。?/td> 1053K
代理商: S1C63466D
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82
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11.5 I/O memory of serial interface
Table 4.11.5.1 shows the I/O addresses and the control bits for the serial interface.
Table 4.11.5.1 Control bits of serial interface
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF45H
PUL13
PUL12
PUL11
PUL10
R/W
PUL13
PUL12
PUL11
PUL10
1
On
Off
P13 pull-up control register
functions as a general-purpose register when SIF (slave) is selected
P12 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF (master) is selected
SCLK (I) pull-up control register when SIF (slave) is selected
P11 pull-up control register (ESIF=0)
functions as a general-purpose register when SIF is selected
P10 pull-up control register (ESIF=0)
SIN pull-up control register when SIF is selected
R/W
FF72H
SD3
SD2
SD1
SD0
SD3
SD2
SD1
SD0
2
High
Low
MSB
Serial I/F transmit/receive data (low-order 4 bits)
LSB
R/W
FF73H
SD7
SD6
SD5
SD4
SD7
SD6
SD5
SD4
2
High
Low
MSB
Serial I/F transmit/receive data (high-order 4 bits)
LSB
0
Slave
2
OSC1/2
1
PT
3
OSC1
[SCS1, 0]
Clock
[SCS1, 0]
Clock
FF71H
SDP
SCPS
SCS1
SCS0
R/W
SDP
SCPS
SCS1
SCS0
0
MSB first LSB first Serial I/F data input/output permutation
Serial I/F clock phase selection
–Negative polarity (mask option)
–Positive polarity (mask option)
Serial I/F
clock mode selection
FF70H
0
SCTRG
ESIF
RR/W
0 3
SCTRG
ESIF
2
0
Trigger
Run
SIF
Invalid
Stop
I/O
Unused
Serial I/F clock trigger (writing)
Serial I/F clock status (reading)
Serial I/F enable (P1 port function selection)
FFE3H
0
EISIF
RR/W
0 3
EISIF
2
0
Enable
Mask
Unused
Interrupt mask register (Serial I/F)
FFF3H
0
ISIF
RR/W
0 3
ISIF
2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Interrupt factor flag (Serial I/F)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
ESIF: Serial interface enable register (P1 port function selection) (FF70HD0)
Sets P10–P13 to the input/output port for the serial interface.
When "1" is written: Serial interface
When "0" is written: I/O port
Reading: Valid
When "1" is written to the ESIF register, P10, P11, P12 and P13 function as SIN, SOUT, SCLK, SRDY,
respectively.
In the slave mode, the P13 terminal functions as SRDY output terminal, while in the master mode, it
functions as the I/O port terminal.
At initial reset, this register is set to "0".
Note: After setting ESIF to "1", wait at least 10 sec before starting actual data transfer since a hazard
may be generated from the P12 (SCLK) terminal when ESIF is set to "1".
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