參數(shù)資料
型號: S1C63466D
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC140
封裝: DIE-140
文件頁數(shù): 130/135頁
文件大?。?/td> 1053K
代理商: S1C63466D
86
EPSON
S1C63466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)
4.12 Sound Generator
4.12.1 Configuration of sound generator
The S1C63466 has a built-in sound generator for generating buzzer signals.
Hence, generated buzzer signals (BZ) can be output from the BZ terminal.
Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it
permits the adding of a digital envelope by means of duty ratio control. It also has a one-shot output
function for outputting key operated sounds.
Figure 4.12.1.1 shows the configuration of the sound generator.
fOSC1
BZ
output circuit
Programmable
dividing circuit
256 Hz
One-shot buzzer
control circuit
Duty ratio
control circuit
BZFQ0–BZFQ2
BDTY0–BDTY2
Buzzer output
control circuit
Envelope
addition circuit
ENON
BZE
ENRTM
ENRST
BZSTP
BZSHT
SHTPW
Fig. 4.12.1.1 Configuration of sound generator
Note: The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and
times that are described in this section are the values in the case of crystal oscillation (32.768 kHz,
Typ.), they differ when CR oscillation (60 kHz, Typ.) is selected.
4.12.2 Mask option
Polarity of the BZ signal output from the BZ terminal can be selected as either positive polarity or
negative polarity by mask option. Figure 4.12.2.1 shows each output circuit configuration and the output
waveform.
When positive polarity is selected, the BZ terminal goes to a low (VSS) level when the BZ signal is OFF.
Select positive polarity when driving a piezo buzzer by externally connecting an NPN transistor.
When negative polarity is selected, the BZ terminal goes to a high (VDD) level when the BZ signal is OFF.
Select negative polarity when driving a piezo buzzer by externally connecting a PNP transistor.
VDD
VSS
BZ signal
BZ terminal
VDD
VSS
BZ signal
BZ terminal
(a) When positive polarity is selected
(b) When negative polarity is selected
Fig. 4.12.2.1 Configuration of output circuit
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