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參數(shù)資料
| 型號： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 87/145頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-34
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.7 Serial Interface (SIN, SOUT, SCLK)
4.7.1 Configuration of serial interface
The S1C60N08 Series has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.7.1.1.
The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of 3
types of master mode (internal clock mode: when the S1C60N08 Series is to be the master for serial
input/output) and a type of slave mode (external clock mode: when the S1C60N08 Series is to be the
slave for serial input/output).
Also, when the serial interface is used at slave mode, SIOF signal which indicates whether or not the
serial interface is available to transmit or receive can be output to output port R11 by mask option.
SD0–SD7
SCS0
SCS1
SE2
Output
latch
EISIO
Serial I/F
interrupt control
circuit
ISIO
SIOF
SCTRG
Serial I/F
activating
circuit
System clock
Serial clock
counter
Serial clock
selector
Shift register (8 bits)
Serial clock
generator
SOUT
SIN
SCLK
Fig. 4.7.1.1 Configuration of serial interface
4.7.2 Master mode and slave mode of serial interface
The serial interface of the S1C60N08 Series has two types of operation mode: master mode and slave mode.
In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates
this internal clock at the SCLK terminal and controls the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK terminal and uses it as the synchronous clock to the built-in shift register.
The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address
2F2HD2, D3).
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.7.2.1.
Table 4.7.2.1 Synchronous clock selection
SCS1
0
1
SCS0
0
1
0
1
Mode
Master mode
Slave mode
Synchronous clock
CLK
CLK/2
CLK/4
External clock
CLK: CPU system clock
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as
follows:
At master mode, after output of 8 clocks from the SCLK terminal, clock output is automatically sus-
pended and SCLK terminal is fixed at low level.
At slave mode, after input of 8 clocks to the SCLK terminal, subsequent clock inputs are masked.
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