參數(shù)資料
型號(hào): S1C60N08F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 70/145頁
文件大?。?/td> 1118K
代理商: S1C60N08F0A0100
I-18
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler)
4.3.3 OSC3 oscillation circuit
In the S1C60N08 Series, the S1C60A08 has twin clock specification. The mask option enables selection of
either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's subclock source.
Because the oscillation circuit itself is built-in, it provides the resistance as an external element when CR
oscillation is selected, but when ceramic oscillation is selected both the ceramic oscillator and two
capacitors (gate and drain capacitance) are required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
VDD
OSC4
OSC3
CDC
CGC
Oscillation circuit control signal
Ceramic
To CPU
(and serial interface)
OSC4
OSC3
R
CR
CCR
Oscillation circuit control signal
To CPU
(and serial interface)
R
FC
R
DC
S1C60A08
CR oscillation circuit
Ceramic oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
As indicated in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the
resistor (RCR) between terminals OSC3 and OSC4 when CR oscillation is selected. When 82 k
is used for
RCR, the oscillation frequency is about 410 kHz. When ceramic oscillation is selected, the ceramic oscilla-
tion circuit can be configured by connecting the ceramic oscillator (Typ. 500 kHz) between terminals
OSC3 and OSC4 to the two capacitors (CGC and CDC) located between terminals OSC3 and OSC4 and
VDD. For both CGC and CDC, connect capacitors that are about 100 pF. To lower current consumption of
the OSC3 oscillation circuit, oscillation can be stopped through the software.
For the S1C60N08 and S1C60L08 (single clock specification), do not connect anything to terminals OSC3
and OSC4.
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