參數(shù)資料
型號(hào)： S1C60A13F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.2 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁(yè)數(shù)： 57/104頁(yè)
文件大?。?/td> 850K
代理商： S1C60A13F
48
EPSON
S1C60N13 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.9 Clock Timer
4.9.1 Configuration of clock timer
The S1C60N13 Series has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator.
The clock timer is configured of a seven-bit binary counter that serves as the input clock, a 256 Hz signal
output by the divider. Data of the four high-order bits (16 Hz–2 Hz) can be read out by the software.
Figure 4.9.1.1 is the block diagram for the clock timer.
32 Hz, 8 Hz, 2 Hz
256 Hz
Clock timer reset signal
Interrupt request
OSC1
oscillation
circuit
Watchdog
timer
Divider
Data bus
128 Hz–32 Hz
16 Hz–2 Hz
Interrupt
control
Clock Timer
Fig. 4.9.1.1 Clock timer block diagram
Ordinarily, this clock timer is used for all types of timing functions such as clocks.
4.9.2 Interrupt function
The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set
whether to mask any of these frequencies.
Figure 4.9.2.1 is the timing chart of the clock timer.
Clock timer timing chart
Frequency
Register
Address
2E0H
D0
16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
32 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
Fig. 4.9.2.1 Clock timer timing chart
As shown in Figure 4.9.2.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz , 2
Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Selection of whether
to mask the separate interrupts can be made with the interrupt mask registers (ETI32, ETI8, ETI2).
However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the
falling edge of the corresponding signal.
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