參數(shù)資料
型號： S1C60A13F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.2 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁數(shù)： 22/104頁
文件大?。?/td> 850K
代理商： S1C60A13F
16
EPSON
S1C60N13 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
4.2 Resetting Watchdog Timer
4.2.1 Configuration of watchdog timer
The S1C60N13 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz
signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3
or 4 seconds, the initial reset signal is output automatically for the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
Clock timer
TM0–TM3
2 Hz
Watchdog timer
WD0–WD2
Initial reset signal
OSC1 demultiplier
(256 Hz)
Watchdog timer
reset signal
Fig. 4.2.1.1 Watchdog timer block diagram
The watchdog timer, configured of a three-bit binary counter (WD0–WD2), generates the initial reset
signal internally by overflow of the MSB.
Watchdog timer reset processing in the program's main routine enables detection of program overrun,
such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is
incorporated where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial
reset signal restarts operation.
4.2.2 Mask option
You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen,
there is no need to reset the watchdog timer.
4.2.3 Control of watchdog timer
Table 4.2.3.1 lists the watchdog timer's control bits and their addresses.
Table 4.2.3.1 Control bits of watchdog timer
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
2EFH
WDRST
WD2
WD1
WD0
WR
WDRST3
WD2
WD1
WD0
Reset
0
Reset
–
Watchdog timer reset
Timer data (watchdog timer) 1/4 Hz
Timer data (watchdog timer) 1/2 Hz
Timer data (watchdog timer) 1 Hz
5 Undefined
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
WDRST: Watchdog timer reset (2EFHD3)
This is the bit for resetting the watchdog timer.
When "1" is written : Watchdog timer is reset
When "0" is written : No operation
Read-out : Always "0"
When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after
this. When "0" is written to WDRST, no operation results.
This bit is dedicated for writing, and is always "0" for read-out.
4.2.4 Programming note
When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data
(WD0–WD2) cannot be used for timer applications.
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