參數(shù)資料
型號(hào): S1C60A13F
元件分類(lèi): 微控制器/微處理器
英文描述: 4-BIT, MROM, 1.2 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, QFP14-80
文件頁(yè)數(shù): 41/104頁(yè)
文件大?。?/td> 850K
代理商: S1C60A13F
S1C60N13 TECHNICAL MANUAL
EPSON
33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.7.3 Master mode and slave mode of serial interface
The serial interface of the S1C60N13 Series has two types of operation mode: master mode and slave
mode.
In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates
this internal clock at the SCLK (P12) terminal and controls the external (slave side) serial device.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK (P12) terminal and uses it as the synchronous clock to the built-in shift register.
The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address
2F2HD2, D3).
When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in
Table 4.7.3.1.
Table 4.7.3.1 Synchronous clock selection
SCS1
0
1
SCS0
0
1
0
1
Mode
Master mode
Slave mode
Synchronous clock
CLK
CLK/2
CLK/4
External clock
CLK: CPU system clock
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as
follows:
At master mode, after output of 8 clocks from the SCLK (P12) terminal, clock output is automatically
suspended and SCLK (P12) terminal is fixed at low level.
At slave mode, after input of 8 clocks to the SCLK (P12) terminal, subsequent clock inputs are masked.
Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous
clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1
fOSC3)
should not be performed.
A sample basic serial input/output portion connection is shown in Figure 4.7.3.1.
S1C60N13
Master mode
Slave mode
SCLK (P12)
SOUT (P11)
SIN (P10)
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C60N13
SCLK (P12)
SOUT (P11)
SIN (P10)
R11(SIOF)
External
serial device
CLK
SOUT
SIN
Input terminal
Fig. 4.7.3.1 Sample basic connection
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