參數(shù)資料
型號(hào)： RH80530GZ009512
元件分類： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 14/89頁(yè)
文件大小： 1672K
代理商： RH80530GZ009512
Mobile Intel
Pentium
III Processor-M Datasheet
14
Datasheet
298340-002
2.1.6
Signal Differences Between the Mobile Pentium III Processor
(in BGA2 and Micro-PGA2 Packages) and the Mobile Intel
Pentium III Processor-M
A list of new and changed signals is shown in Table 1.
Table 1. New and Revised Mobile Intel Pentium III Processor-M Signals
Signals
Function
BCLK, BCLK# Differential host clk signals.
CLKREF
Host Clock reference signal in Single Ended Clocking mode.
BSEL[1:0]
Signals are output only instead of I/O. Please refer to the Appendix for details.
DPSLP#
Deep Sleep pin (replaces SLP# pin on the Pentium III processor).
NCTRL
AGTL output buffer pull down impedance control.
VID[4:0]
Voltage Identification (different implementation from Pentium III processor). Please refer to
Section 3.2.3 for details.
VTTPWRGD
Power Good signal for VCCT, which indicates that, the VID signals are stable. Please refer to
Figure 3 for VTTPWRGD system level connections.
2.2
Power Management
2.2.1
Clock Control Architecture
The Mobile Pentium
III
Processor-M clock control architecture (Figure 1) has been optimized for
leading edge mobile computer designs. The clock control architecture consists of six different clock
states: Normal, Auto Halt, Quick Start, HALT/Grant Snoop, Deep Sleep and Deeper Sleep states. The
Auto Halt state provides a low-power clock state that can be controlled through the software execution
of the HLT instruction. The Quick Start state provides a very low power and low exit latency clock
state that can be used for hardware controlled “idle” computer states. The Deep Sleep and Deeper
Sleep states provide extremely low-power states that can be used for “Power-On-Suspend” computer
states, which is an alternative to shutting off the processor’s power. The exit latency of the Deep Sleep
state is 30
μ
sec in the Mobile Pentium
III
Processor-M. Performing state transitions not shown in
Figure 1 is neither recommended nor supported. Table 2 provides the clock state characteristics, which
are described in detail in the following sections.
2.2.2
Normal State
The Normal state of the processor is the normal operating mode where the processor’s core clock is
running and the processor is actively executing instructions.
2.2.3
Auto Halt State
This is a low-power mode entered by the processor through the execution of the HLT instruction. A
transition to the Normal state is made by a halt break event (one of the following signals going active:
NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, or SMI#).
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