參數(shù)資料
型號(hào): RD28F6408W30B85
廠商: INTEL CORP
元件分類: 存儲(chǔ)器
英文描述: 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA80
封裝: 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁(yè)數(shù): 4/82頁(yè)
文件大?。?/td> 749K
代理商: RD28F6408W30B85
28F320W30, 28F3204W30, 28F6408W30, 28F640W30
iv
Preliminary
6.0
Flash Erase Mode
....................................................................................................27
6.1
Block Erase.........................................................................................................27
6.2
Erase Protection (V
PP
< V
PPLK
)..........................................................................28
Flash Suspend/Resume Modes
..........................................................................28
7.1
Program/Erase Suspend.....................................................................................28
7.2
Program/Erase Resume......................................................................................28
Flash Security Modes
.............................................................................................29
8.1
Block Lock...........................................................................................................29
8.2
Block Unlock .......................................................................................................30
8.3
Lock-Down Block ................................................................................................30
8.4
Block Lock Operations during Erase Suspend....................................................30
8.5
WP# Lock-Down Control.....................................................................................30
Flash Protection Register
.....................................................................................32
9.1
Protection Register Read....................................................................................32
9.2
Program Protection Register...............................................................................32
9.3
Protection Register Lock.....................................................................................33
Power and Reset Considerations
......................................................................34
10.1
Power-Up/Down Characteristics .........................................................................34
10.2
Power Supply Decoupling...................................................................................34
10.3
Flash Reset Characteristics................................................................................34
Electrical Specifications
........................................................................................35
11.1
Absolute Maximum Ratings ................................................................................35
11.2
Extended Temperature Operation.......................................................................35
11.3
DC Characteristics..............................................................................................36
11.4
Discrete Capacitance (32-Mbit VF BGA Package) .............................................38
11.5
Stacked Capacitance (32/4 and 64/8 Stacked-CSP Package) ...........................39
Flash AC Characteristics
......................................................................................40
12.1
Flash Read Operations.......................................................................................40
12.2
Flash Write Operations .......................................................................................49
12.3
Flash Program and Erase Operations.................................................................51
12.4
Reset Operations................................................................................................51
SRAM AC Characteristics
.....................................................................................53
13.1
SRAM Read Operation .......................................................................................53
13.2
SRAM Write Operation........................................................................................55
13.3
SRAM Data Retention Operation........................................................................56
Ordering Information
..............................................................................................58
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
Appendix A
Appendix B
Appendix C
Flash Write State Machine (WSM)
................................................................59
Flowcharts
.............................................................................................................61
Common Flash Interface
.................................................................................68
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