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Page xlviii of liv
45.3.10
Data Register (CE_DATA)............................................................................. 2501
45.3.11
Interrupt Flag Register (CE_INT)................................................................... 2502
45.3.12
Interrupt Enable Register (CE_INT_EN) ....................................................... 2509
45.3.13
Status Register 1 (CE_HOST _STS1) ............................................................ 2512
45.3.14
Status Register 2 (CE_HOST _STS2) ............................................................ 2513
45.3.15
DMA Mode Setting Register (CE_DMA_MODE)......................................... 2516
45.3.16
Card Detection/Port Control Register (CE_DETECT) ................................... 2517
45.3.17
Special Mode Setting Register (CE_ADD_MODE)....................................... 2519
45.3.18
Version Register (CE_VERSION) ................................................................. 2520
45.4
Interrupt Requests ........................................................................................................... 2521
45.5
DMA Specifications ....................................................................................................... 2522
45.5.1
DMA for Buffer Writing................................................................................. 2522
45.5.2
DMA for Buffer Reading................................................................................ 2522
45.6
Operation ........................................................................................................................ 2523
45.6.1
Command/Response Formats ......................................................................... 2523
45.6.2
Data Block Format.......................................................................................... 2524
45.6.3
Buffer Structure and Buffer Accesses............................................................. 2525
45.6.4
Automatic CMD12 Issuance........................................................................... 2527
45.6.5
Operation in the Case of Error/Timeout ......................................................... 2528
45.7
Examples of Setting ........................................................................................................ 2529
45.7.1
Legends........................................................................................................... 2529
45.7.2
Command Transmission ................................................................................. 2530
45.7.3
Command Transmission
→ Response Reception........................................... 2531
45.7.4
Command Transmission
→ Response Reception (with Response Busy)....... 2532
45.7.5
Single-Block Read .......................................................................................... 2534
45.7.6
Multi-Block Read ........................................................................................... 2535
45.7.7
Multi-Block Read (with Automatic CMD12 Issuance) .................................. 2536
45.7.8
Single-Block Write ......................................................................................... 2537
45.7.9
Multi-Block Write .......................................................................................... 2538
45.7.10
Multi-Block Write (with Automatic CMD12 Issuance) ................................. 2539
45.7.11
Forcible Termination ...................................................................................... 2540
45.7.12
Setting Values of CE_CMD_SET .................................................................. 2541
45.8
Usage Note ..................................................................................................................... 2543
45.8.1
Card Detection ................................................................................................ 2543
Section 46 Motor Control PWM Timer........................................................... 2545
46.1
Features........................................................................................................................... 2545
46.2
Input/Output Pins............................................................................................................ 2547
46.3
Register Descriptions...................................................................................................... 2548
46.3.1
PWM Control Register_n (PWCR_n) (n = 1, 2)............................................. 2549