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Page li of liv
49.2.11
Software Reset Control Register 1 (SWRSTCR1).......................................... 2700
49.2.12
Software Reset Control Register 2 (SWRSTCR2).......................................... 2702
49.2.13
System Control Register 1 (SYSCR1) ............................................................ 2703
49.2.14
System Control Register 2 (SYSCR2) ............................................................ 2704
49.2.15
System Control Register 3 (SYSCR3) ............................................................ 2705
49.2.16
System Control Register 4 (SYSCR4) ............................................................ 2707
49.2.17
System Control Register 5 (SYSCR5) ............................................................ 2708
49.2.18
On-Chip Data-Retention RAM Area Setting Register (RRAMKP)................ 2710
49.2.19
Deep Standby Control Register (DSCTR) ...................................................... 2711
49.2.20
Deep Standby Cancel Source Select Register (DSSSR) ................................. 2713
49.2.21
Deep Standby Cancel Edge Select Register (DSESR).................................... 2716
49.2.22
Deep Standby Cancel Source Flag Register (DSFR) ...................................... 2718
49.2.23
XTAL Crystal Oscillator Gain Control Register (XTALCTR)....................... 2721
49.3
Operation ........................................................................................................................ 2722
49.3.1
Sleep Mode ..................................................................................................... 2722
49.3.2
Software Standby Mode.................................................................................. 2723
49.3.3
Software Standby Mode Application Example............................................... 2726
49.3.4
Deep Standby Mode........................................................................................ 2727
49.3.5
Module Standby Function............................................................................... 2733
49.3.6
Adjustment of XTAL Crystal Oscillator Gain ................................................ 2733
49.4
Usage Notes .................................................................................................................... 2734
49.4.1
Usage Notes on Setting Registers ................................................................... 2734
49.4.2
Usage Notes when the Realtime Clock is not Used ........................................ 2734
Section 50 User Debugging Interface ..............................................................2735
50.1
Features........................................................................................................................... 2735
50.2
Input/Output Pins............................................................................................................ 2736
50.3
Description of the Boundary Scan TAP Controller ........................................................ 2737
50.3.1
Bypass Register (BSBPR)............................................................................... 2737
50.3.2
Instruction Register (BSIR) ............................................................................ 2737
50.3.3
Boundary Scan Register (SDBSR) ................................................................. 2738
50.3.4
ID Register (BSID) ......................................................................................... 2744
50.4
Description of the Emulation TAP Controller ................................................................ 2745
50.4.1
Bypass Register (SDBPR) .............................................................................. 2745
50.4.2
Instruction Register (SDIR) ............................................................................ 2745
50.5
Operation ........................................................................................................................ 2747
50.5.1
TAP Controller ............................................................................................... 2747
50.5.2
Reset Configuration ........................................................................................ 2748
50.5.3
TDO Output Timing ....................................................................................... 2748
50.5.4
User Debugging Interface Reset ..................................................................... 2749